1. Field of the Invention
This invention relates generally to the automated synthesis of logic circuits by a data processing system and more particularly, to the inclusion in the logic circuit synthesis of criteria relating to the timing delays in the circuit that impact the performance of the synthesized circuits.
2. Description of the Related Art
At the frequency at which modern logic circuits, and particularly data processing systems, have been designed to operate, the importance of many properties of the circuits, that previously could be ignored, have become important. One such property is the timing delays found for the components of the logic circuit. The simultaneous presence of a plurality of signals at a predetermined location in the data processing system can be an essential element in the operation of a circuit. Because the signals typically pass through circuit components and travel a finite distance along the conducting leads, the required simultaneity of the signals may not exist.
Referring next to FIG. 1, the procedure for synthesizing a logic circuit design according to the prior art is shown. Model definition data structures from a library of component definitions are entered into the data structures associated with the synthesis data base in step 11. In step 12, the information related to the instances of the circuit design, including the connectivity information, is entered in the data base. The instances of the circuit design are generally in a behavioral or functional form when entered in the synthesis data base. The synthesis procedure relates the design instances of the circuit design to the model instances in step 13. In step 14, a set of rules for the synthesis procedure is applied to each of the model instances and the model instances are altered and connected in such a way as to maximize certain parameters such as size, path delay, power, etc. In step 15, the resulting circuit design is placed in a format that can control the automated fabrication of the circuit.
The foregoing procedure suffers from a lack of flexibility, particularly o timing parameters. Typically, a model instance or component will find a single definition in the model definition library. Associated with each model definition is a timing delay that will be found in the resulting synthesized circuit. Even when a plurality of possible model instances are available to replace the original model instance, the automatic synthesis procedure typically does not have the capability to select a component based on the timing delays. In fact, the capability is not present to determine conveniently that a timing problem is present. Furthermore, the critical paths in which the timing delays are providing the most serious problems can not be automatically identified.
A need has, therefore, been felt for a synthesis procedure that can incorporate timing criteria automatically and for timing criterion that can be conveniently used by the synthesis procedure.